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Neuromorphic Devices

Task1 investigates innovative logic and memory devices for extremely lower power device and neuromorphic device applications. Our research focus on technologies to overcome the limit of von Neumann Machines at materials and device levels.

1) Novel resistance switching memory

Novel resistance switching memory will be demonstrated, and highly integrated array devices will be fabricated to demonstrate the functionality.

  • 1 step: Optimized ReRAM device fabricate
  • 2 step: Kbit Cross-point memory cell array
  • 3 step: CMOL type device and Neuromorphic device simulation and demonstration

The cross-point array architecture is expected to offer the highest integration density with the non-volatility, high operation speed and lower power consumption. But cross-point array architecture is a severe parallel connection system which requires embedding of the selection devices, such as diode, to prevent the interference between the neighboring cells during the operation.
Prof. H. Hwang (GIST) has been leading the ReRAM project of non-volatile memory program funded by Ministry of Knowledge and Economy. His group published the most advanced results in recent 5 years.

read interference cross-talk between cells distribution cells leakage current effect gd203 8x8 cell array, cu-c 32x32 cell array voltage[v]/

2) NEMS-CMOS hybrid device and circuit technology demonstration

Graphene will be used as an electrode material for NEMS to overcome the limitation of of CNT electrode, and graphene NEMS-CMOS hybrid devices will be used to demonstrate extreme low power logic circuit module with 100 times lower operation/standby power.

  • 1 step: Graphene electrode demonstration
  • 2 step: Graphene NEMS devices fabrication
  • 3 step: Circuit demonstration utilized to fabricate grapheme NEMS devices

graphene cmos nems/

Prof. B.H. Lee (SEMATECH) has worked on graphene MOSFET project funded by DARPA as a co-PI responsible for device fabrication at SEMATECH and worked as a lead integrator for IBM 65nm high performance logic applications and has an in-depth knowledge on device integration and circuit design. His expertise will be utilized to fabricate graphene NEMS devices. He also served as a co-director of Front End Process transition center funded by Science Research Corporation and SEMATECH during 2004-2006

3) Organic flexible memory device
  • 1 step: Organic flexible memory device fabrication
  • 2 step: Operational mechanism and characteristic analysis
  • 3 step: Optimizing the highly integrated matrix structure based on flexible substrate

top-gate fet

Prof. T.H. Lee (GIST) has presented outstanding results in nanowire devices and organic flexible memory devices recently. The collaboration with foreign faculty members will enhance the research significantly.

 
 
 

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